Skip to main content
University of Wisconsin–Madison
Research into novel solutions to complex computing problems

JING (JANE) LI, PhD

li_jingDugald C. Jackson Faculty Scholar & Assistant Professor

Department of Electrical and Computer Engineering

Department of Computer Science (affiliated)

Phone: (608) 890-3975

jli AT ece.wisc.edu
janeli AT cs.wisc.edu

 
 
Dr. Jing Li is an assistant professor and Dugald C. Jackson Faculty Scholar at the department of Electrical and Computer Engineering. She is also affiliated with Computer Science department.
 
She spent her early career at IBM T. J. Watson Research Center as a Research Staff Member after obtaining her PhD degree from Purdue University in 2009. Her general research interest is developing new computing paradigm, driven either by technologies (from bottom-up) or by workloads (from top-down) or by both. Her primary area of interests is “everything about memory” with a strong emphasis on “design for transformation”, including but are not limited to near-/in-memory computing, associative/cognitive computing, reconfigurable computing and programming model, design automation, IC design, architecture-aware algorithm design, and evolving applications, which can transform today’s hardware-software hierarchy. In addition to modelings and simulations, additional emphasis is put on real hardware demonstration through architecting, designing and testing new hardware prototypes both at chip level and system level.
 
She is the recipient of prestigious DARPA’s Young Faculty Award (one out of 26 nationwide) in 2016 and WARF Innovation Awards (WIA) Finalist (6 out of 400+ patents), IBM Research Division Outstanding Technical Achievement Award in 2012 for successfully achieving CEO milestone, multiple invention achievement awards and high value patent application awards from IBM from 2010-2014, IBM Ph.D. Fellowship Award in 2008, Meissner Fellowship in 2004 from Purdue University, etc.
 
She has been serving on the technical committee for International Electron Devices Meeting (IEDM), Design Automation Conference (DAC), International Conference on Computer‑Aided Design (ICCAD) and International Symposium on Microarchitecture (MICRO) (external), etc..  She serves as the general chair/ technical chair/finance chair/publicity chair for a premier industry memory conference – International Memory Workshop (IMW) and co-organizes it with Intel/Micron/SK Hynix/CEA LETI to hold annual meetings with worldwide memory vendors.

 

Selected Honors

  • Dugald C. Jackson Faculty Scholar  of Electrical and Computer Engineering  (named after the first department chair of ECE), University of Wisconsin-Madison, 2017
  • DARPA Young Faculty Award, Defense Advanced Research Projects Agency (one of the 26 recipients nationwide), 2016
  • WARF Innovation Awards (WIA) Finalist, University of Wisconsin-Madison (6 out of 400++ patents), 2016
  • VLSI Transactions Best Paper Award, IEEE Circuits and Systems Society, 2013
  • Outstanding Research Division Technical Achievement Award (A-level, for successfully achieving CEO milestone on Storage Class Memory), IBM T. J. Watson, 2012
  • IBM High Value Patent Application Awards, IBM T. J. Watson, 2014
  • IBM Invention Achievement Awards, IBM T. J. Watson, 2010-15
  • IBM PhD Fellowship Award, 2008-09
  • The Dean’s and Semester Honors for Outstanding Scholastics Performance, Purdue University, 2007-08.
  • Magoon Award for Excellence in Teaching, Purdue University, 2005-06
  • Meissner Fellowship Award, Electrical and Computer Engineering department, Purdue University, 2004-05.

SELECTED INVITED TALKS (external)

  1. “Enabling Nonvolatile Memory for Data-Centric Computing: Technology, Circuit and System,” Panasonic Corp., 4:00pm to 5:00pm, Kyoto, Japan, July 16th, 2015
  2. “Enabling Phase-change Memory for Data-Centric Computing: Technology, Circuit and System,” Special session at IEEE international Symposium on Circuits and Systems (ISCAS), Lisbon, May 25th, 2015
  3. “Emerging-Materials-Enabled Devices for Data-Centric Computing,” Special guest lecture co-sponsored by CTO, APTD, and WPDN, Applied Materials, 3:00pm – 4:00pm PST, August 27th, 2014
  4. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Colloquium of Electrical and Computer department at Purdue University, 3:00pm – 4:00pm EST, April 28th, 2014
  5. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Colloquium of Electrical and Systems department at University of Pennsylvania, 11:00am – 12:00pm EST, March 17th, 2014
  6. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Electrical Engineering Seminar Series at Harvard University, 3:00pm – 4:00pm EST, March 7th, 2014
  7. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Electrical and Computer Engineering Department Seminar at University of Illinois Urbana-Champaign (UIUC), 4:00pm – 5:00pm CST, March 3rd, 2014
  8. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Computer Engineering Seminar at University of California Santa Barbara (UCSB), 11:00am – 12:00pm PST, February 12th, 2014
  9. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Joint CSSI and CALCM Seminar Series at Carnegie Mellon University (CMU), 12:00pm – 1:00pm EST, 1st, 2013
  10. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Electrical Engineering Seminar Series at University of California, Los Angeles (UCLA), 1:00pm – 2:30pm PDT, Oct 28th, 2013
  11. “Data Centric Computing in Emerging Technologies: A PCM-CMOS Hybrid Hardware Accelerator,” Electrical Engineering Seminar Series at Princeton University, 12:30pm – 1:30pm EST, Oct 16th, 2013
  12. “A Holistic View of Architecting Storage Class Memory into Future System,” Invited tutorial on system-technology interaction, International Memory Workshop (IMW), Milan, Italy, May 20, 2012
  13. “Resistance Drift in Phase Change Memory,” The IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, April 19, 2012
  14. “Phase Change Memory,” The Connecticut Microelectronics and Optoelectronics Consortium (CMOC) Twenty-First Annual Symposium, Storrs, CT, April 11, 2012
  15. “Phase Change Memory Design: Challenges and Opportunities,” China Semiconductor Technology International Conference (SEMICON China), Shanghai, China, March 15-17, 2011
  16. “Design Challenges in Multi-Level Phase Change Memory,” New Non-Volatile Memory Workshop (NNVMW’10), Industrial Technology Research Institute (ITRI), Hsin-chu, Taiwan 11, 2010
  17. “Robust Design in Emerging Technologies,” Intel Corporation, CA, 2:00 pm-3:30 pm PDT, Feb.1,2008
  18. “A Genetic and Reconfigurable Test Paradigm Using Low-Cost Integrated Poly-Si TFT,” LSI Corporation, CA, 1:30 pm-3:30 pm PDT, Oct.19, 2007

Other Professional activities:

  • General Chair/Technical Chair/Finance Chair/Publicity Chair  at International Memory Workshop (annual meeting with world-wide memory vendors, co-organized w/ Intel, Micron, SK-Hynix, CEA LETI), 2013-Present
  • TPC of ICCAD’17, ICCAD’16, MICRO’16 (external), IEDM’17, IEDM’16, ISCAS’17, ISCAS’16, ISLPED’17, DAC’14, DAC’13, DAC’12
  • Micro MBA, for perspective business/technical leaders at IBM, 2011